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The Truth About Chip Sizes: Why “2nm” Doesn’t Mean What You think
The numbers you hear about silicon wafer sizes and chip manufacturing processes,like “3nm” or “2nm,” are more marketing terms than actual measurements. Predictions from the Interuniversity Microelectronics Center (IMEC) suggest that TSMC’s 2nm chipsets and Intel Foundry’s 18A and 14A process technologies are on track,with A14 (1.4nm) chips expected by 2027 and A10 (1nm) nodes by 2029. IMEC even anticipates the possibility of 0.2mm silicon as early as 2039.
However, these numbers don’t accurately reflect the physical dimensions of the transistors on the chip.We may not see a true 10nm barrier broken until the late 2030s. Here’s the breakdown.
Silicon wafer Sizes: Perception vs. Reality
The 2nm and 1.8nm silicon technologies being developed aren’t actually 2nm in thickness, nor do they represent the distance between transistors. Chip manufacturers use these numbers to refer to the minimum feature size achievable during fabrication, which is more of a process node
name* than a physical measurement.
(Image credit: IMEC)
Since around 1997, silicon process node names have been largely symbolic. For example, Intel’s 250nm process node had a gate length of 200nm, a practice that continued until 2011.
“silicon process node names have been inaccurate”
TSMC and Samsung adopted similar “perception marketing” in 2018 with their 7nm process nodes, which had gate lengths comparable to Intel’s 10nm silicon. Current 3nm chips have a gate length of 16-18nm and a metal pitch of about 23nm.True 10nm silicon may not appear until IMEC’s predicted sub-A2 chipset generation in 2039.
The Interplay of Wafer Size and Moore’s Law
Moore’s Law observes that the number of transistors on an integrated circuit doubles approximately every two years. As silicon wafers shrink,so do transistors,but physical limitations eventually come into play.
Moore’s Law is an observation, not a hard rule. Semiconductors can only get so small before heat becomes a major design challenge.
Nvidia’s CEO, Jensen Huang, has expressed skepticism about continuing Moore’s Law due to thermal constraints in graphics cards. However, CPUs like Intel’s Lunar Lake chipset have more potential for size reduction.
IMEC’s insights into silicon wafer sizes, along with advancements in chip interconnect architecture and transistor technology, suggest that Moore’s law remains achievable.While the long-term future is uncertain, current projections are promising.
The potential transistor count on sub-A2 (10nm) chipsets is significant. While the current Intel Core Ultra 9 285K has around 18 billion transistors,sub-A2 chipsets could potentially house around 300 billion transistors by 2039.
