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Intel Unveils Advanced Chip Packaging Technologies for Next-Gen AI Processors

At the IEEE electronic Components and Packaging Technology Conference (ECTC), Intel revealed its progress in developing innovative chip packaging technology designed to facilitate larger, more powerful processors tailored for artificial intelligence applications.

As Moore’s Law decelerates, manufacturers of advanced GPUs and data center chips are increasingly focused on expanding silicon area to meet the growing computational demands of AI. With single silicon chip sizes capped at approximately 800 square millimeters, these manufacturers are adopting advanced packaging technologies to integrate multiple silicon components, effectively creating a unified, high-performance chip.

Intel’s recent announcements at ECTC highlighted three key innovations aimed at overcoming limitations in silicon integration and package size. These include advancements in interconnect technology for adjacent silicon dies, a more precise method for bonding silicon to package substrates, and a system designed to enlarge critical package components for improved heat dissipation. These technologies collectively enable the integration of over 10,000 square millimeters of silicon within a package exceeding 21,000 mm², an area roughly equivalent to four and a half credit cards.

EMIB Technology Receives 3D Enhancement

A critically important constraint in maximizing silicon integration within a single package involves connecting numerous silicon dies along their edges. While organic polymer package substrates offer a cost-effective interconnection solution, silicon substrates provide higher connection densities.

Intel’s EMIB (Embedded Multi-die Interconnect Bridge) technology,introduced over five years ago,addresses this by embedding a small silicon sliver within the organic package beneath the adjoining edges of silicon dies. This EMIB is etched with fine interconnects, boosting connection density beyond the capabilities of organic substrates.

The latest iteration, EMIB-T, features not only the standard fine horizontal interconnects but also incorporates relatively thick vertical copper connections known as through-silicon vias (TSVs). These TSVs enable direct power connections from the circuit board below to the chips above, bypassing the EMIB and minimizing power loss. Additionally, EMIB-T includes a copper grid that functions as a ground plane, reducing power noise caused by fluctuating workloads from process cores and other circuits.

“It sounds simple,but this is a technology that brings a lot of capability to us,” says Rahul Manepalli,vice president of substrate packaging technology at Intel.

Advancements in thermal Management

Another technology showcased by Intel at ECTC is low-thermal-gradient thermal compression bonding, an evolution of existing methods for attaching silicon dies to organic substrates. This process involves positioning micrometer-scale solder bumps on the substrate to connect with a silicon die.The die is then heated and pressed onto these microbumps, melting them to establish interconnects between the package and the silicon.

due to differing thermal expansion rates between silicon and the substrate, engineers must limit the inter-bump distance, or pitch. This expansion difference also complicates the creation of large, reliable substrates filled with numerous silicon dies, a critical requirement for AI processors.

According to Manepalli, Intel’s new technology makes the thermal expansion mismatch more predictable and manageable, facilitating the population of very large substrates with dies. This technology can also be used to increase the connection density to EMIB, achieving a density of approximately one connection every 25 micrometers.

Improved Heat Spreader design

As silicon assemblages grow in size, they generate more heat, necessitating efficient heat dissipation. An integrated metal component called a heat spreader is crucial for this, but creating one large enough for these packages presents challenges. Warping of the package substrate and imperfections in the heat spreader’s flatness can prevent it from making full contact with the hot dies. Intel’s solution involves assembling the integrated heat spreader in multiple parts, incorporating extra stiffening components to maintain flatness and ensure consistent contact.

“Keeping it flat at higher temperatures is a big benefit for reliability and yield,” says Manepalli.

While Intel states that these technologies are still in the R&D phase and has not announced commercial release dates, they are expected to be crucial for competing with TSMC’s planned packaging expansion in the coming years.