Huawei has filed a patent for a quad-chiplet design that may be used for its next-generation AI accelerator known as the Ascend 910D. Huawei’s quad-chiplet design certainly mimics Nvidia’s approach for its quad-chiplet Rubin Ultra, but there is one more engaging thing in that patent around Huawei’s plans for its advanced chip packaging – it appears that Huawei is developing techniques that could rival market-leader TSMC’s advanced packaging tech. This could eventually enable the company to sidestep US sanctions adn catch up to Nvidia’s AI GPU performance more quickly.

That detail is,of course,in the patent that describes how a quad-chiplet processor could be made. While we cannot say without a doubt that it is indeed the Ascend 910D, we can certainly connect some dots and make an assumption about the possible part (even though the patent, of course, does not indicate that). It also aligns with current chip industry insider chatter that suggests a quad-chiplet 910D is in the works.

Perhaps a more interesting part about the rumored Ascend 910D is the interconnection between the compute chiplets, which appear like bridges (TSMC’s CoWoS-L or Intel’s EMIB with Foveros 3D) rather than ‘just’ an interposer (at least from the patent point of view). Meanwhile, a processor designed for AI training ought to be accompanied by a bunch of HBM-class memory modules, and these modules may use an interposer-class interconnection.

While SMIC and Huawei are certainly behind in terms of lithography, they might be on par with TSMC in terms of packaging. That woudl be a key growth that would help China sidestep the impact of US export restrictions that bar access to leading-edge chip manufacturing. Instead, Chinese companies could simply use advanced packaging to tie together multiple chiplets using older process node technology, enabling them to match, or at least come close to, the performance of chips made with leading-edge process nodes.