New 3D Chip Stacking Method Overcomes Semiconductor Limitations
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Scientists in Tokyo have created a 3D chip-stacking technique that significantly boosts memory bandwidth and reduces energy consumption in next-generation computing.
Researchers have unveiled a groundbreaking 3D chip stacking method that promises to revolutionize computing architectures. The new technique, developed by scientists, addresses limitations in traditional semiconductors by enhancing memory bandwidth and power efficiency.
The core of this innovation is a chip-on-wafer (COW) process that achieves a narrow chip-to-chip spacing of 10 μm and a minimal mount loading time of less than 10 milliseconds.
According to Chujo, “More than 30,000 chips of various sizes were fabricated onto the waffle wafer, achieving enhanced bonding speed without any chip-detachment failures,” explaining the COW process.
To facilitate this precise and high-speed COW process,the research team focused on resolving thermal stability issues that can impact multilevel stacking of ultra-thin wafers.By carefully designing the chemical properties, they created a new adhesive material, DPAS300, suitable for both COW and wafer-on-wafer processes. Experimental studies demonstrated that this organic-inorganic hybrid adhesive possesses important adhesiveness and heat resistance.
Enhanced Memory Bandwidth and Power Integrity
To maximize memory bandwidth and improve the power integrity of BBCube, the scientists implemented a 3D xPU-on-DRAM architecture supported by a new power distribution highway. This involved embedding capacitors between xPU and DRAM, implementing redistribution layers on the waffle wafer, and placing through-silicon vias in wafer lanes and DRAM scribe lines.
“These innovations reduced the energy required for data transmission to one-fifth to one-twentieth of that in conventional systems.”
“These innovations reduced the energy required for data transmission to one-fifth to one-twentieth of that in conventional systems, while also suppressing power supply noise to below 50 mV,” states Chujo, emphasizing the advantages of the 3D stacked computing architecture.
the chip integration technologies developed by researchers have the potential to transform next-generation computing architectures.
