SAN JOSE, California – (BUSINESS WIRE) – May 14, 2019–
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced extensive support for memory technologies in a wide range of advanced Samsung Foundry process technologies for high-bandwidth applications. As a result of the long collaboration with Samsung Foundry, Cadence has recorded DDR5 / 4 PHY IP on the Samsung 7nm Low Power Plus process (7LPP), GDDR6 PHY IP on the Samsung 14nm Low Power Plus (14LPP) process and 2.4G High-Bandwidth Memory 2 ( HBM2) PHY IP on the Samsung 10nm Low Power Plus (10LPP) process, which has been redefined as an 8nm Low Power Plus (8LPP) process. In addition, Cadence ® PHY IP for GDDR6 achieved silicon success in the Samsung 7LPP process. Ordinary customers can start creating projects using Samsung Foundry's advanced process technologies with the certainty that the IP of the Cadence DRAM interface is ready for use.
For more information on the IP Cadence for GDDR6 PHY and DDR5 / 4, visit www.cadence.com/go/samsungddrip. For more information on the IP Cadence for HBM2 PHY, visit www.cadence.com/go/samsunghbm2ip.
The IP Cadence that supports the various advanced nodes of Samsung Foundry is destined to different emerging application areas, including HPC (high-performance computing), artificial intelligence (AI), IoT, graphics, automatic driving (AD) and adaptive driver assistance systems (ADAS). Customers benefit from access to a complete solution for a single supplier for controllers, PHYs and IP Verification (VIP) that accelerates chip integration times and reduces interoperability risks. Other key competitive advantages include:
- Cadence design techniques reuse the technology of Cadence-tested DDR and SerDes designs, resulting in lower risk in the implementation of advanced memory technologies
- Cadence's low bit error rate (BER) for GDDR6 IP reduces memory bus attempts, giving applications greater bandwidth and lower maximum latency
- Cadence's design margin allows users to implement GDDR6 on PCBs using standard FR4 fiberglass materials, reducing the cost of GDDR6 distribution
- Cadence's reference design for memory interfaces allows users to replicate the results of the Cadence test chip in their products
- Cadence DRAM controllers are based on the industry-leading Dali Denali ® controller, which includes a complete set of features for popular memory interfaces
"The success of Cadence silicon and the tapeout in Samsung Foundry's 7LPP, 8LPP, 10LPP and 14LPP technologies are milestones in our successful collaboration, which allows us to offer high performance IP DDR5 / 4 PHY, GDDR6 PHY and HBM2 solutions to common customers, "said Jaehong Park, executive vice president of Design Platform Development at Samsung Electronics. "Customers who design on advanced nodes now have a range of Cadence DRAM interface IPs to choose from, as part of the extensive DRAM interface enablement in Samsung Foundry processes."
"Samsung Electronics is a leader in state-of-the-art memory technologies, where we have consistently been the first to allow the most advanced memory solutions," said Harry Yoon, vice president of Memory Product Planning & Application Engineering at Samsung Electronics . "In collaboration with Cadence, we will continue to expand our premium memory lineups with high performance, high capacity and low power consumption to support the growing demand for advanced high bandwidth applications, including HPC, AI and ADAS."
"Using the latest technologies from Samsung Electronics, we continue to drive the innovation of advanced nodes as demonstrated by our successful GDDR6 PHY IP silicon and our latest DDR5 / 4 PHY, GDDR6 PHY and HBM2 IP tapeouts," he said. Amjad Qureshi, vice president, R & D, Design IP at Cadence. "Our mutual customers can access all the simulation and emulation data required to ensure that the projects work as expected, and we're ready to engage customers now."
Customers using Samsung's advanced nodes and IP Cadence can obtain the following performance specifications:
- GDDR6 technology using Cadence IP allows up to 512 Gbit / sec between the host CPU and a single GDDR6 die
- HBM2 technology using Cadence IP allows bandwidth up to 2400 Gbit / sec between the host CPU and a single stack of HBM2
- DDR5 technology using Cadence IP allows up to 128 GB of DRAM per channel
Cadence PHY IP for GDDR6, DDR5 / 4 and HBM2, as well as memory models, are now available for customer commitments. Design files are also ready for selected customers to begin integration work.
Information on Cadence
Cadence enables electronic systems and semiconductor companies to create innovative end products that are transforming the way people live, work and play. Cadence software, IP hardware and semiconductors are used by customers to deliver products to the market faster. The company's System Design Enablement strategy helps customers develop differentiated products, from chips to cards to systems, in the mobile, consumer, cloud data center, automotive, aerospace, IoT, industrial and other sectors. Cadence is listed among the 100 best Fortune Magazine companies to work for. More information on cadence.com.
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SOURCE: Cadence Design Systems, Inc.
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PUB: 14/05/2019 06:15 PM / DISC: 05/14/2019, 06:15 PM